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Strong Tier-1 brand and metro location increase competition, but niche senior EDA+ML role limits applicant density.
Role requires specialized EDA and semiconductor domain knowledge, making cross-industry transfers difficult.
Explicit 10+ years, mandatory ML/software skills, and EDA experience make screening highly restrictive.
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Lead exploration and development of AI/ML methodologies and tools to improve ASIC design efficiency and quality (power, performance, area, verification) for SoC and IP teams.
Collaborate closely with architecture, IP design, SoC design, verification, implementation, and design enablement teams to pilot and integrate AI/ML solutions into advanced node SoC projects, including Edge-AI, Automotive Processors, and microcontrollers.
Develop prototypes and apply state-of-the-art AI/ML techniques such as GenAI, Reinforcement Learning, Graph Neural Networks, focused on automating and enhancing VLSI CAD and ASIC design processes.
10+ years of experience in complex software development projects.
Degree: BS or MS in Computer Science, Electrical Engineering, Computer Engineering, or related disciplines with strong software development background.
Strong programming skills in Python and C++, with hands-on Unix/Linux experience.
Work Experience Required: 10+ years; notice period: Not explicitly mentioned in the JD.
Demonstrated expertise in AI/ML applications specifically targeting VLSI CAD and ASIC design automation workflows.
Experience working with cross-functional teams spanning architecture, IP, SoC design, verification, and implementation in advanced semiconductor technologies.
Background includes understanding of design constraints, EDA tools, and software development for optimization problems relevant to semiconductor design and implementation.