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Tier-1 brand, mid-level experience requirement, and Bangalore location increase competition.
Highly specialized SoC and CPU architecture skills limit cross-industry transferability.
Explicit years plus niche SystemC, C++ and SoC modeling requirements make shortlisting highly strict.
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Research and develop methodologies and infrastructure for SoC performance modeling and analysis.
Model proposed micro-architecture in performance models to identify bottlenecks and suggest solutions.
Collaborate with architecture, design, and validation teams to productize performance improvements and ensure expected benefits in the product.
Experience: B.Tech +5 years or M.Tech +3 years or Ph.D. with internships in related areas.
Strong C++ or object-oriented programming skills; experience with C++/SystemC TLM modeling.
Expertise in computer architecture or strong understanding of data structures/algorithms or deep learning applied to architecture.
Experience with SoC sub-systems such as cache, memory, or fabric, and performance model/analysis for complex SoCs.
Proven ability to drive research ideas into practical SoC performance improvements and collaborate cross-functionally.
Background in performance modeling and analysis of complex SoC components with focus on latency, bandwidth, and power.
Familiarity with bringing up/integrating performance or functional simulators and involvement with validation/scripting environments is advantageous.