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Tier-1 brand plus Bangalore metro but highly niche senior CAD specialization reduces applicant density.
Role requires deep ASIC CAD, synthesis, STA, and EDA tool expertise, making cross-industry transferability low.
Explicit 15+ years requirement and mandatory toolchain, synthesis, and LEC expertise enforce strict shortlisting.
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Lead the development and deployment of RTL Synthesis Reference Flows across advanced technology nodes (5nm, 3nm, 2nm+).
Drive RTL-to-Gate optimization to improve Power, Performance, and Area (PPA) collaborating closely with RTL and Physical Design teams.
Own Logic Equivalence Checking (LEC) flows, Static Timing Analysis (STA) signoff processes, and manage relationships with EDA vendors for tool roadmap and deployment.
15+ years of experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Expertise with Synopsys Fusion Compiler/Design Compiler and Cadence Genus synthesis tools.
Hands-on experience with Logic Equivalence Checking tools (Cadence Conformal LEC, Synopsys Formality) and Static Timing Analysis (PrimeTime).
Proven ability to lead synthesis methodology development and cross-functional collaboration across design and physical teams at a senior level.
Strong scripting skills in Tcl and Python for automation of synthesis and signoff flows.
Experience with low power design methodologies (UPF/CPF), physical synthesis, and AI/ML-driven CAD tool innovations is a strong advantage.