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Strong employer and metro location increase applicants, but niche ASIC verification skills limit broader competition.
Highly specialized semiconductor verification skills limit transferability across industries.
Explicit years, mandatory UVM/SystemVerilog, SoC and gate-level simulation requirements create strict technical screening.
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Develop and execute comprehensive verification test plans and test cases for SoC designs across RTL simulation, FPGA prototyping, and emulation platforms.
Perform gate-level simulations and debugging to ensure design quality and reliability, including DFX Verification and generating functional patterns for wafer sorting and post-silicon testing.
Collaborate with design, architecture, and firmware teams to define and advance coverage-driven verification methodologies, including development of UVM and PSS verification environments.
Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering.
4-8 years of relevant experience in SoC verification, specifically with processor-based SoCs (ARM, RISC-V, ARC).
Proficiency in C, SystemVerilog, UVM, coverage-driven verification methodologies, and experience with DFX Verification and functional pattern generation for post-silicon testing.
Experience with bus protocols (AXI, AHB, APB), interfaces (PCIe, DDR, UART, I2C, I2S, SPI), and scripting languages such as Python, Perl, TCL, or BASH.
Experienced in building and enhancing UVM-based verification methodologies for complex SoC designs involving processor cores and multiple bus protocols.
Skilled at advanced verification environments with hands-on capabilities in test-bench development, scoreboards/checkers implementation, and gate-level and power-aware simulations.
Capable of collaborating across multiple teams (design, architecture, firmware) to drive verification strategy and improve verification efficiency through coverage analysis.