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Niche senior ASIC DV role with specialized EDA skills reduces applicant competition despite Ericsson's brand.
Requires deep ASIC verification and EDA expertise specific to semiconductor domain, limiting cross-industry transferability.
Explicit 10+ years, mandatory SystemVerilog/UVM, EDA tool and CI experience create stringent shortlisting filters.
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Develop and lead next-generation Front-End CAD methodologies and DV flows for ASIC IP and SoC development within a global silicon engineering team.
Drive optimization and innovation of verification methodologies and EDA workflows, including deployment, support, and troubleshooting of complex front-end DV tools and flows.
Collaborate across design, verification, and manufacturing teams to ensure methodology alignment and enhance silicon quality and verification productivity, with an emphasis on AI/ML applications in design and verification.
10+ years of relevant experience in ASIC design verification.
Deep expertise in SystemVerilog and UVM testbench architecture at IP, ASIC, or SoC level.
Proficiency in scripting languages such as Python, Perl, or shell scripting and experience with front-end EDA tools including Verilog simulators and formal verification.
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field from recognized institution.
Experienced in driving methodology and tool development in a distributed, multi-site R&D environment for advanced silicon technologies (5G/6G).
Demonstrates strong ownership over complex infrastructure challenges and leads innovation in verification processes, including AI/ML-driven enhancements.
Skilled in integrating CI methodologies and collaborating across design, verification, and manufacturing teams for scalable and long-term solutions.