Back
Tier-1 brand plus metro location but niche specialization yields medium competition.
Specialized mixed-signal IP verification skills are industry-specific, so background fit sensitivity is high.
Explicit 5-10 years, mandatory SystemVerilog/UVM, coverage and simulation tools imply high strictness.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own end-to-end functional verification flow for DDR PHY IP including test plan creation, testbench architecture, test bench creation, design validation, and micro-architectural implementation verification.
Automate validation tasks and perform debugging of issues in pre-silicon environment at IP, subsystem, and SoC levels to ensure design meets specifications for performance, power, and functionality.
Collaborate with digital, analog, RTL, and physical design teams to improve verification methodologies and drive functional verification closure.
BS or MS degree with 5-10 years of industry experience in design verification, SystemVerilog and OVM/UVM.
Experienced in validation flow including testbench architecture, test plan creation, verification closure, waveform debug, functional and code coverage, VCS simulation tools.
Work location: Bangalore, India; Hybrid work model (on-site and off-site).
Work Experience Required: 5-10 years in relevant design verification.
Deep expertise in DDR PHY IP verification and knowledge of Design for Testability (DFx) features.
Skilled in scripting (Python/Perl) and familiar with version control tools such as Git, VSCode, GitHub CoPilot or other AI tools.
Capable of multitasking and collaborating across multiple geographically distributed teams with strong debugging and problem-solving skills.