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Niche ASIC verification skills and seniority limit applicant density despite metro location.
Semiconductor RTL and UVM verification skills are highly domain-specific and not easily transferable.
Explicit 8+ years and mandatory SystemVerilog/UVM/RISC-V processor verification requirements increase filter strictness.
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Create and execute verification plans and test benches for RISC-V based application-specific IP within ARM Cortex M4 based ASICs.
Drive the functional verification process including test case development, coverage analysis, assertions, and coordination with IP developers to ensure design correctness and completeness.
Serve as the single point of contact for IP verification and enable tapeout for Enphase control ASICs in 22nm technology.
At least 8 years of hands-on experience in logic IP verification using System Verilog.
Proficiency in UVM, System Verilog, Verilog, C, Python, and HW/SW interface verification.
Strong understanding and practical experience with RISC-V architecture, processor verification, and associated toolchains (compiler, assembler, simulator).
Work is onsite 3 days a week in Bangalore, India, with a plan to transition to full 5-day in-office schedule.
Experienced in complex SoC verification processes that include secure processor boot code and floating point instruction implementation in microcontroller-based ASICs.
Able to manage full lifecycle of IP bring-up from verification through tapeout and production in advanced technology nodes (22nm).
Proficient with both directed and random testing methodologies, as well as generating functional test vectors for post-silicon validation.