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Niche semiconductor EDA skillset reduces applicants but Tier-1 brand and metro location increase competition.
Highly specialized PERC/Calibre and semiconductor physical-verification skills have low transferability across industries.
Explicit 10+ years requirement plus mandatory PERC/Calibre and scripting/toolchain expertise create strict filters.
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Lead development, validation, and release of Calibre PERC rule decks addressing ESD, latch-up, power-domain, connectivity, and reliability verification.
Drive PERC flow enablement for IP, block, subsystem, and SoC design stages integrating with LVS and extraction for physical verification signoff.
Develop automation scripts, debug complex issues with cross-functional teams, and mentor junior engineers to build team competency.
BTech/BE/ME/MTech in Electronics & Communication, Electrical Engineering, Microelectronics, VLSI, or related discipline.
At least 10 years of relevant industry experience in PERC rule development and physical verification flows.
Strong hands-on expertise with Calibre LVS/PERC tools, scripting languages (TCL, Perl, Python, SKILL), and knowledge of analog/mixed-signal design flows.
Experience working collaboratively across multiple teams and time zones for complex design verification projects.
Experienced in translating technology and product requirements into scalable PERC checks and methodologies for signoff readiness.
Proven ability to lead physical verification flows across multiple design levels with strong problem-solving and debugging skills.
Capable of driving automation, establishing best practices, and mentoring others in a cross-functional, multi-site design enablement environment.