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Tier-1 employer and Bengaluru location increase applicants, but niche EDA/ASIC skillset limits competition.
Requires specialized ASIC/EDA methodology and tool experience, limiting cross-industry transferability.
Mandatory 5+ years and specific EDA tools, scripting, and ASIC methodology requirements.
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Own deployment and continuous improvement of front-end ASIC design methodologies including SoC integration, LEC, CDC/RDC, SDC, and linting processes.
Automate design check flows to enhance operating efficiency and collaborate globally to resolve design check violations and sign-off reports.
Represent company in technical conferences and working groups related to design methodology and tool flows.
5+ years of experience in VLSI ASIC design and methodology development.
Expertise with EDA tools: SpyGlass, VC RDC, LEC, Design Compilers, and formal verification tools.
Proficiency in scripting languages: Python, Perl, TCL.
Strong understanding of Verilog/SystemVerilog and front-end design verification techniques (CDC, RDC, Lint, FV, Synthesis).
Proven experience handling complex SoC project design check activities and deploying sophisticated automation flows in ASIC front-end methodologies.
Collaborative experience working with global design teams on methodology definition and improvements.
Technical proficiency aligning with EDA tool usage and scripting to drive operational efficiencies and checks automation.