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Niche EDA skillset and senior 10+ years requirement lower competition despite Tier-1 metro employer.
Highly specific semiconductor PERC/physical verification skills limit cross-industry transferability.
Explicit 10+ years, mandatory PERC/Calibre expertise and scripting make filters highly strict.
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Lead development, validation, and release of Calibre PERC rule decks for ESD, latch-up, power-domain, connectivity, and reliability verification.
Drive PERC flow enablement across IP, block, subsystem, and SoC design stages and integrate with LVS, extraction, and physical verification signoff flows.
Develop and maintain automation scripts, debug complex PERC/LVS issues, and collaborate with cross-functional teams for root-cause analysis and methodology enhancement.
Bachelor's or Master's in Electronics & Communication, Electrical Engineering, Microelectronics, VLSI, or related field.
At least 10 years of relevant industry experience in PERC rule development and physical verification.
Strong hands-on expertise in Calibre LVS/PERC and understanding of CMOS and FinFET technologies.
Proficiency in scripting languages such as TCL, Perl, Python, SKILL, and TVF/SVRF for rule automation and flow development.
Experienced in leading physical verification flows across multiple design hierarchy levels including IP, block, subsystem, and SoC.
Deep domain knowledge of ESD fundamentals, analog/mixed-signal design flows, and reliability verification methodologies.
Able to work effectively across cross-functional, multi-site teams with strong ownership and technical leadership in PERC methodology and rule development.