Back
Tier-1 brand and metro location increase competition, but niche UVM/SystemVerilog skills moderate applicant density.
Highly specialized semiconductor verification skills limit easy transferability across industries.
Mandatory 6+ years plus UVM/SystemVerilog, EDA tools, and protocol expertise enforces stringent shortlisting.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own pre-silicon verification of IP modules, subsystems, and SoC top-level designs to ensure functional correctness and quality silicon delivery.
Define and execute digital verification strategies and plans using UVM-based environments for RTL and gate-level simulations.
Collaborate with cross-functional teams and use verification metrics (functional, code, assertion coverage) to drive verification closure and bug resolution.
Bachelor's or Master's degree in Electrical Engineering (EE).
More than 6 years of hands-on experience in digital verification within a reputed semiconductor design company.
Strong expertise in RTL verification using Verilog/SystemVerilog and Universal Verification Methodology (UVM).
Experience verifying industry-standard interfaces like I2C, SPI, AXI, PCIe, USB, Ethernet and proficiency with simulators such as VCS, Questa, and Xcelium.
Experienced in developing coverage-driven verification plans and managing complex SoC verification projects at subsystem and top-level design.
Proficient in scripting languages (Python, Perl, Tcl, Shell) for automation and debugging in a verification environment.
Capable of multi-disciplinary collaboration with Architecture, Firmware, Software, and Hardware teams to ensure specification and micro-architecture compliance in a semiconductor product development context.