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Niche low-power SoC DV role, mid-level and metro location, moderate candidate competition.
Highly specialized semiconductor DV skills limit transferability across industries.
Explicit 6–8 years and mandatory SystemVerilog/UVM and UPF/CPF skills make filters strict.
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Own end-to-end low-power design verification including testbench development, test cases, assertions, and debugging for complex SoCs.
Validate power intent and low-power features using UPF/CPF methodologies throughout the design lifecycle.
Drive functional and assertion coverage closure and perform power-aware verification in collaboration with RTL, architecture, and physical design teams.
6–8 years of experience in design verification.
Strong skills in SystemVerilog/UVM, assertion-based and coverage-driven verification.
Experience with low-power design techniques including UPF/CPF-based verification and knowledge of SoC low-power constructs (clock gating, isolation, level shifters, retention).
BS/MS degree in Electrical or Computer Engineering or related field.
Experienced in complex SoC low-power verification environments with focus on power intent validation.
Proficient in advanced verification methodologies including assertion usage and coverage-driven approaches.
Able to debug complex RTL/UPF issues and collaborate effectively across architecture, RTL, and physical design teams.