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Tier-1 employer and metro location increase competition, while niche verification skills and seniority limit applicant density.
Highly specialized SoC verification skills (SystemVerilog, UVM, coverage-driven verification) limit cross-industry transferability.
Explicit 10–15 year requirement plus mandatory SystemVerilog/UVM expertise and leadership makes screening highly stringent.
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Lead and manage a high-performing Design Verification team responsible for IP and SoC verification across multiple projects, ensuring on-time delivery and high-quality silicon.
Drive verification planning, execution, functional coverage closure, regression management, and sign-off while collaborating with cross-functional global teams.
Champion adoption of advanced verification techniques including AI-assisted workflows, improve methodologies, and mentor engineers to build scalable verification capabilities.
B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or related field.
10–15 years of experience in Design Verification with expertise in IP, subsystem, and SoC verification.
Proven experience leading Design Verification teams in a multi-site environment with hands-on skills in SystemVerilog, UVM, assertions, constrained-random verification, functional coverage, and regression management.
Strong understanding of verification planning, testbench architecture, debug methodologies, and verification metrics.
Experienced in managing complex verification projects and multiple program execution with strong technical leadership in SoC/IP verification domains.
Skilled in driving verification methodology improvements and automation including reusable UVM environments and scalable regression infrastructure.
Ability to operate cross-functionally with global teams and champion innovation using AI-assisted verification tools and advanced debug techniques.