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Tier-1 brand plus mid-level seniority but highly specialized EDA skillset limits applicant density.
Role requires niche EDA/place-and-route expertise, making cross-industry transferability low.
Explicit years, mandatory place-and-route/Innovus experience, and advanced-node expertise make filters strict.
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Develop and maintain high-performance place-and-route CAD flow tools and methodologies for custom CPU physical design.
Collaborate globally with CPU physical design teams to provide methodology guidance, support tools/flows, and resolve project-specific implementation issues.
Engage with EDA vendors to influence tool development roadmaps and troubleshoot tool-related problems.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years experience OR Master's degree with 5+ years OR PhD with 4+ years in Hardware Engineering or related.
7+ years hands-on experience in place-and-route of high-performance chips in design or CAD roles.
Proficiency in Tcl and Python scripting; experience with automation and physical design tasks including place-and-route, analysis, timing sign-off, and PDV.
Experience with advanced technology nodes (5nm or lower) and industry-standard place-and-route tools like Cadence Innovus.
Experienced engineering professional specializing in CPU physical design CAD with deep knowledge of implementation flows and PPA (power, performance, area) optimization.
Technical leader capable of architecting methodology improvements and managing regression of place-and-route flows.
Skilled collaborator who can effectively partner with global CPU design teams and external EDA vendors to deliver superior silicon outcomes.