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Tier-1 brand, metro location and mid-to-senior level increase competition despite niche skillset.
Highly specialized semiconductor EDA and STA tooling skills limit transferability across industries.
Explicit 5–15 years, degree requirements and mandatory STA/CAD tooling experience make shortlisting highly stringent.
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Build and support static timing analysis (STA) tools and flows to ensure custom CPUs meet leading power, performance, and area targets.
Architect and recommend methodology improvements for silicon power, performance, and area optimization.
Maintain, debug, and support STA and timing closure flows, resolving project-specific issues and working closely with global CPU physical design teams and EDA vendors.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years experience OR Master's with 5+ years OR PhD with 4+ years in Hardware Engineering or related domain.
5 to 15 years of relevant experience explicitly required.
Experience with STA, timing closure flows, and physical CPU design support.
Not explicitly mentioned in the JD: Notice period, location constraints, or specific certifications.
Experienced in CPU physical design and STA methodologies with a strong background in power, performance, and area optimization.
Proven ability to collaborate worldwide with CPU design teams and manage relationships with EDA vendors for tool development and issue resolution.
Capable of architecting improvements in static timing analysis tools and methodology to maintain competitive custom CPU implementation.