Back
High—Tier-1 brand, Bengaluru metro, and mid-level 4+yrs increase applicant density despite niche SKILL requirement.
High—specialized pCell, Cadence SKILL, and PDK experience limit cross-industry transferability.
High—mandatory 4+ years, SKILL/pCell expertise, and PDK/DRC-LVS requirements sharply filter candidates.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Design, develop, and maintain complex parameterized cells (pCells) for advanced analog and mixed-signal technologies using SKILL programming.
Manage technology file updates and implement advanced layout features like device abutment, folding, and parameterized arrays to ensure scalable and robust layout automation.
Collaborate with circuit and layout teams to integrate pCells into design flows, ensuring DRC/LVS compliance and support for CAD/methodology automation improvements.
Minimum 4+ years of experience in pCell development and layout automation.
B.Tech or M.Tech degree in Electronics, Electrical Engineering, Microelectronics, or related field.
Strong expertise in Cadence SKILL programming specifically for pCell development.
Experience with technology file customization, layout verification flows (DRC, LVS), and familiarity with Cadence Virtuoso design environment.
Experienced in designing pCells from scratch for multiple technology nodes (e.g., 180nm to 28nm or below).
Demonstrates hands-on knowledge of analog/mixed-signal layout methodologies and device structures such as RF, high-voltage, or MOSFET.
Capable of advancing automation techniques and integrating new features aligned with process design kits and foundry requirements.