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Tier-1 employer and Bangalore location increase applicant density despite niche ASIC specialization.
Highly domain-specific semiconductor flow and integration skills limit cross-industry transferability.
Requires specific ASIC integration, flow methodology, and automation skills, creating strict technical filters.
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Own full-chip and block-level integration processes for multiple NVIDIA SoC and GPU projects, ensuring RTL units are seamlessly connected with proper hierarchy management.
Define and evolve internal ASIC design methodologies to enhance scalability, quality, and turnaround times across projects.
Build automation pipelines (using Python/Perl) for integration, debugging, and delivery; collaborate with cross-functional teams for flow compatibility and drive full-chip debug efforts.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics and Communications, Computer Science, or equivalent.
3+ years experience in ASIC design integration and methodologies.
Comprehensive understanding of IP development and build flows.
Notice Period: Not explicitly mentioned in the JD.
Experienced engineer capable of working across multiple global teams and geographies to influence and collaborate effectively.
Strong hands-on expertise in ASIC methodology, automation, and integration at full-chip and block levels, comfortable with multi-technology nodes.
Skilled in building modular, reusable infrastructure and comfortable mentoring others on flow usage and integration standards.