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Tier-1 brand, metro location, and mid-level experience raise competition; niche SoC validation skills restrict qualified applicants.
Highly domain-specific SoC verification, firmware, and emulation expertise limits cross-industry transferability.
Explicit 4–6 years requirement plus mandatory SystemVerilog, UVM, emulation, protocol and bring-up skills enforce strict screening.
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Own end-to-end SoC verification and validation flows, including planning, execution, and closure of multiple subsystems.
Develop, execute, and sign off on complex verification/validation plans and test cases for pre- and post-silicon validation, including firmware and HAL development.
Debug and root cause analysis of SoC issues using emulation platforms and various hardware/software tools, contributing to infrastructure and methodology improvements.
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
4-6 years of experience in SoC pre- and post-silicon verification, validation, and bring-up.
Proficient in C programming, embedded systems, SystemVerilog, UVM, and scripting languages such as Python or Perl for test automation.
Experience with SoC protocols (DDR, PCIe, LPDDR, USB, Ethernet, I2C, I3C, SPI, AXI, AHB, APB) and emulation platforms like Palladium.
Experienced ASIC validation engineer with strong ownership of SoC-level verification flows and multi-domain debugging skills (digital logic, firmware, timing, low-power, DFT).
Comfortable working with advanced verification techniques including constrained-random, assertion-based, and coverage-driven methodologies.
Skilled at developing and maintaining automated infrastructure and performing complex performance and stress testing at SoC and datapath levels.