Back
Niche senior VLSI verification role but Tier-1 brand and Bangalore location increase applicant density.
Specialized SystemC/SystemVerilog verification skills require semiconductor domain experience.
Strict 13+ years requirement plus mandatory SystemC/C++ and verification skills.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Develop and code C++ and SystemC functional models and create associated tests for verification.
Validate developed models using SystemC/SystemVerilog/UVM testbenches and debug issues through collaboration with other teams.
Mentor and lead junior engineers in modeling and verification tasks.
13+ years of relevant experience in functional modeling and verification using C++ and SystemC.
Proficiency in C, C++, SystemC; experience with Python and Verilog/SystemVerilog/UVM is a plus.
Bachelor's or Master's degree in Electronics and Communication or Embedded Systems from a reputed institution.
Experience with development tools such as Visual Studio, Git, and Bitbucket.
Deep expertise in system-level modeling and verification, particularly with C++ and SystemC environments.
Capable of leading debugging and root-cause analysis in firmware and verification test environments.
Experienced in mentoring and leading engineering teams on complex VLSI design and verification tasks.