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Tier-1 brand and Bangalore location but highly specialized ASIC/UVM skillset moderates applicant density.
ASIC verification and UVM/SystemVerilog expertise is highly specialized and not easily transferable across industries.
Explicit 9-13 years plus mandatory UVM/SystemVerilog, C, protocol and gate-level simulation skills enforce strict filtering.
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Drive verification strategy and create test plans and advanced UVM test benches for SoC ASIC verification.
Collaborate across architecture, design, and pre/post-silicon teams to develop and execute verification tests meeting functional coverage goals.
Develop and debug C-based tests, run gate-level and power-aware simulations, and generate functional patterns for automated test equipment (ATE).
9-13 years of experience in ASIC digital verification or related field.
BE or MS degree in Electrical Engineering or Computer Engineering.
Deep knowledge of C, SystemVerilog, UVM, and coverage-driven verification methodology.
Proficiency with bus protocols (APB, AHB, AXI) and scripting languages such as Python, Perl, TCL, and BASH.
Experienced in building and improving UVM-based verification methodologies and complex test benches.
Demonstrated ability to collaborate across multidisciplinary teams including architects, designers, and silicon teams.
Strong debugging skills and hands-on expertise with gate-level/power-aware simulations and SoC-level verification.