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Tier-1 brand and Bangalore metro increase competition, role remains niche and specialized so moderate density.
Mixed-signal verification skills are highly domain-specific to semiconductor/IP verification and not easily transferable.
Explicit years, domain-specific tools, and mandatory verification skills make filtering strict and technical.
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Lead functional verification of mixed signal IPs (e.g. PCIE, USB4 PHYs) including development and execution of test benches and verification plans.
Perform root cause analysis of design failures and collaborate with cross-functional teams to optimize microarchitectural features.
Maintain and enhance verification methodologies and infrastructure using industry-standard tools and scripting for automation.
Bachelor's or Master's degree in Electronics, Communication, Electrical Engineering, VLSI or related field.
Minimum 4+ years experience with Bachelor's or 3+ years with Master's in ASIC/IP verification and subsystem/function coverage.
Proficiency in mixed signal verification using System Verilog, UVM, Verilog and experience with EDA tools like Synopsys VCS, Cadence Xcelium or Mentor Questa.
Strong scripting skills in Python, Perl or Tcl and familiarity with protocols like JTAG, IJTAG, CRI, APB and multi-clock domain designs.
Experienced engineer skilled in both analog behavioral modeling and digital verification methodologies within mixed signal environments.
Demonstrates strong problem solving in root cause analysis and debugging complex mixed signal designs.
Able to drive verification excellence through technical leadership and collaborate effectively with architects, RTL developers, and physical design teams.