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Niche SoC verification skillset and seniority reduce candidate pool and competition.
Highly specialized SoC verification skills (SV/UVM, VIP, formal) transfer poorly across industries.
Specific SV/UVM, formal verification skills and explicit 10–18 years requirement create strict shortlisting filters.
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Lead the architecture and development of reusable testbenches and VIPs using SystemVerilog and UVM for SoC verification.
Drive coverage closure including functional and code coverage, and implement SV assertions and coverage-driven verification strategies.
Lead debug and verification activities across block, subsystem, and full-chip levels, mentoring junior engineers and collaborating with cross-functional teams.
7+ years of experience in ASIC/SoC verification with strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
Proven ability to develop reusable verification environments and VIP from scratch with experience in coverage closure and SV assertions.
Notice Period: Not explicitly mentioned in the JD.
Deep technical expertise in SoC verification lifecycle including formal verification and coverage-driven strategies.
Experience leading verification strategy planning and execution for complex SoC projects in fast-paced environments.
Capable of mentoring junior staff and working collaboratively with design, architecture, and system teams to meet quality and performance goals.