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Niche SystemVerilog/PCIe role limits applicants, but Bengaluru metro and Rambus brand increase competition.
Highly specialized RTL verification and PCIe protocol expertise limits cross-industry transferability.
Mandatory 7+ years, PCIe protocol requirement, and SystemVerilog/UVM skills create high shortlisting strictness.
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Develop and maintain testbenches and test sequences for verifying new PCIe and CXL controller technologies and features.
Plan and implement functional coverage and augment test suites to achieve coverage goals.
Manage regression testing including development, monitoring, debugging, and correcting test environments and RTL controller designs.
Bachelor’s degree or higher in Electrical Engineering or Computer Science.
At least 7 years of experience in HDL logic design and verification.
Proficiency in System Verilog / UVM testbenches and Verilog/System Verilog RTL design.
Experience with PCI-Express controller and protocol is mandatory.
Experienced in leading pre-silicon verification for complex PCIe or similar controller IP cores.
Skilled in scripting languages such as Python and TCL to enhance verification environments.
Capable of handling regression test cycles and debugging RTL designs effectively in a fast-paced product development setting.