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Niche RTL/SystemVerilog and PCIe expertise required, senior profile reduces applicant pool despite Bangalore location.
Highly domain-specific RTL verification and PCIe protocol expertise limits cross-industry transferability.
Mandatory 7+ years and required SystemVerilog/UVM plus PCIe protocol experience enforce strict screening.
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Develop and maintain testbenches and test sequences for pre-silicon verification of PCIe Controller SoftIP technologies.
Plan and implement functional coverage and enhance test suites to meet coverage goals.
Manage regression testing including development, monitoring, debugging, and correction related to controller RTL design and verification environment scripting.
Bachelor's degree or higher in Electrical Engineering or Computer Science.
Minimum 7 years experience in HDL logic design and verification, including SystemVerilog/UVM and RTL design fluency.
Pre-existing experience or familiarity with PCI-Express controller and protocol.
Preferred experience with Python and TCL scripting languages.
Experienced in leading verification for controller SoftIP technologies, specifically PCIe and related protocols.
Strong hands-on skills in SystemVerilog/UVM testbench development and RTL design verification.
Comfortable working in a hybrid onsite/offsite environment at Bengaluru location.