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Niche MLIR/IREE compiler expertise limits applicants despite Tier-1 brand and metro locations.
Deep compiler, MLIR, and accelerator expertise makes skills highly domain-specific and less transferable.
Explicit 3-12 years plus mandatory IREE/MLIR, NPU compiler/runtime and C/C++ skills drive high filtering.
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Lead design and development of AI/ML compiler and runtime software targeting RISC-V IP, NPU, and SoC platforms.
Develop and optimize IREE-based compiler flows including MLIR lowering, custom dialects, passes, code generation, and runtime integration for efficient edge AI workload execution.
Collaborate cross-functionally with architecture, hardware, firmware, and product teams for bringing up AI workloads on simulators, FPGA, emulators, and silicon, while providing technical leadership and support.
3-12 years of software engineering experience in compiler, runtime, embedded software, or AI/ML systems.
Strong hands-on expertise with IREE, LLVM, MLIR compiler infrastructure including development of MLIR dialects, passes, codegen, and backend integration for custom hardware.
Proficiency with AI model formats/frameworks such as PyTorch, ONNX, TensorFlow Lite and related MLIR lowering concepts like torch-mlir, TOSA, Linalg, quantization dialects.
Strong C/C++ programming skills and experience with Linux development environments including debugging, profiling, build systems, and runtime bring-up.
Experienced in AI compiler/runtime stacks for edge or accelerator-backed AI inference with deep understanding of neural network optimization techniques (quantization, fusion, tiling, memory planning).
Proven capability to lead and mentor engineers and coordinate across hardware-software teams for software architecting and execution of complex modules.
Familiarity with hardware acceleration platforms (NPU, DSP, vector/matrix processors), and runtime/hardware co-design concepts enabling efficient AI execution on edge devices.