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Tier-1 employer and Bangalore metro increase competition, but niche FPGA/ASIC specialization limits applicants.
High because FPGA/emulation and hardware/firmware co-verification skills are industry-specific and not easily transferable.
High due to explicit seniority requirement and mandatory niche FPGA/emulation/platform expertise.
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Lead setup, configuration, and stabilization of advanced FPGA prototyping and emulation platforms during early project phases.
Serve as primary resolver for system-level failures by diagnosing issues across hardware, FPGA/emulator configuration, and early boot code.
Develop automation and monitoring tools to improve reliability and throughput of emulation and prototyping infrastructure, and document troubleshooting methods.
14–19 years of relevant experience in pre-silicon development, hardware verification, or platform bring-up.
Demonstrated expertise with large-scale FPGA prototyping platforms (e.g., Synopsys HAPS) and emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu).
Strong Python scripting skills for tool development and debugging automation.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
Broad systems-level knowledge combining firmware, silicon design, and hardware validation with strong focus on platform bring-up and co-verification.
Experienced in system-level debugging using industry tools (JTAG, protocol analyzers, logic analyzers) across multiple domains.
Skilled at working directly with firmware engineers to remove blockers and improving platform utility in complex hardware/software environments.