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Specialized verification skillset reduces pool, but Bengaluru metro location and known employer increase competition.
Highly domain-specific semiconductor verification expertise limits cross-industry transferability.
Explicit 10+ year requirement and specialized SystemVerilog/UVM protocol expertise make filters highly strict.
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Lead verification strategy and execution for next-generation connectivity IPs and SoCs including CXL, PCIe, and Ethernet within AI and cloud infrastructure.
Architect and develop scalable UVM/SystemVerilog verification environments, drive coverage closure, and ensure first-pass silicon success across multiple programs.
Mentor verification teams, define methodologies and reusable frameworks, and collaborate cross-functionally from architecture through silicon bring-up.
Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering or related field.
Minimum 10+ years of Design Verification experience at Principal level.
Strong proficiency in SystemVerilog and UVM, constrained-random verification, assertions (SVA), coverage-driven methodologies, and RTL debugging.
Experience verifying at least one of: CXL (2.x/3.x), PCIe (Gen4/5/6), Ethernet (10G–800G), with simulator tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Experienced technical leader capable of defining and owning large-scale verification programs for complex SoCs or connectivity IPs in AI infrastructure or hyperscale data center domains.
Strong cross-functional collaborator skilled at early design influence, customer-facing debug, and silicon bring-up support.
Has a track record of delivering multiple first-pass silicon successes and driving verification methodology innovation and reusable IP frameworks.