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Niche semiconductor verification role with specialized protocols reduces competition despite metro location.
Highly specialized DV skills (SystemVerilog, UVM, CXL/PCIe) limit cross-industry transferability.
Explicit 6–12+ years, mandatory SystemVerilog/UVM and protocol expertise make candidate filters stringent.
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Lead verification of complex digital IPs and SoC subsystems from specification through tape-out to ensure high-quality first-pass silicon.
Own verification planning, environment development, test execution, debugging, and verification sign-off while managing schedules and quality commitments.
Collaborate cross-functionally with Architecture, Design, Firmware, Emulation, and Validation teams to drive verification across multiple projects.
6–12+ years of experience in Design Verification.
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
Strong expertise in SystemVerilog and UVM with experience in constrained-random and coverage-driven verification environments.
Experience verifying one or more of these protocols: CXL, PCI Express (Gen4/Gen5/Gen6), Ethernet (10G–400G).
Demonstrated ability to independently lead verification efforts of complex IPs or SoC subsystems, successfully delivering multiple silicon tape-outs.
Strong practical skills in debugging RTL and protocol issues, and developing reusable verification components using SystemVerilog and UVM.
Experience or familiarity with verification for AI infrastructure or data center technologies and working knowledge of SoC-level integration.