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Senior, niche AMS verification role at a known semiconductor firm in Bangalore yields moderate applicant competition.
Highly specialized analog/mixed-signal verification skills limit transferability across industries.
Mandatory 8+ years, MSEE, Verilog-A/SystemVerilog, Cadence and semiconductor process knowledge make screening highly strict.
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Perform end-to-end analog/mixed-signal verification of RFICs from block level to full-chip integration, ensuring comprehensive coverage and adherence to project schedules.
Develop Verilog-A and SystemVerilog Real Number Modeling (RNM) behavioral models, perform equivalence checks, and optimize models for accuracy and simulation efficiency.
Define and execute verification plans derived from product specifications and collaborate closely with design teams to provide feedback on functionality and performance.
Master's degree in Electrical Engineering (MSEE) with 8+ years of related experience.
Hands-on analog/mixed-signal design experience, including LDOs, PORs, ADCs, voltage-current references, and oscillators.
Experience in creating and verifying Verilog-A and SystemVerilog RNM behavioral models for analog circuits.
Proficiency with EDA tools such as Cadence Virtuoso and ADS; knowledge of semiconductor process technologies (CMOS, GaAs/Silicon HBT, SOI, BiCMOS).
Experienced engineer with strong analog/mixed-signal verification expertise at the circuit and system level, capable of building scalable and reusable verification methodologies.
Demonstrates deep understanding of custom analog/mixed-signal circuits and semiconductor technologies, with ability to translate specifications into comprehensive verification plans.
Skilled in behavioral modeling, verification tools, and collaboration with design teams to optimize product functionality and performance.