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Strong Tier-1 brand, metro location, and mid-level experience increase candidate competition significantly.
Highly specialized semiconductor PDK, Calibre and extraction skills limit cross-industry transferability.
Role mandates specific EDA tools, PDK/PEX expertise and a 5+ years minimum, making filters strict.
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Maintain and improve physical verification flows and methodologies including DRC, LVS, ERC, PERC, ESD, Latch-up, and Antenna checks.
Develop, customize and integrate parasitic extraction flows using StarRC, Calibre-xACT, and QRC tools.
Support design teams in solving physical verification and parasitic extraction challenges to facilitate IP release and chip tapeouts, collaborating with tool vendors and foundries.
Minimum 5 years of hands-on experience in a PDK role related to physical verification and parasitic extraction.
Bachelor's degree (minimum) in Computer Science, Electrical/Electronics Engineering, or related field with at least 3+ years of relevant hardware engineering experience (or higher degree with reduced experience accordingly).
Proficiency in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna checks and expertise in StarRC/Calibre-xACT/QRC flow customization.
Working knowledge of programming/scripting languages such as SKILL, Python, Unix shell, Perl, and TCL.
Experienced in developing and modifying custom design rules and checks from scratch or existing runsets for large scale integrated circuit design validation.
Demonstrated capability to revamp and streamline parasitic extraction flows, with hands-on skills in field solvers and RC reduction tools.
Comfortable working in a collaborative team environment interfacing with design teams, tool vendors, and foundries with deep understanding of FinFET, Planar, SOI, and PMIC technologies.