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Tier-1 employer and metro location but niche PCIe/UVM specialization limits applicant density.
Specialized ASIC/SoC verification skills transfer poorly outside semiconductor and hardware design industries.
Multiple mandatory verification technologies, protocol expertise, and explicit years requirement make filters highly stringent.
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Develop and maintain UVM-based verification environments and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
Perform block-level and top-level verification activities, including assertion-based verification, functional coverage, and regression testing to ensure design correctness and coverage closure.
Collaborate with RTL designers, architects, and validation teams; implement and enhance verification components; mentor junior engineers; and contribute to verification methodology improvements.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years experience; OR Master's degree with 3+ years experience; OR PhD with 2+ years experience in Hardware Engineering or related work.
Strong proficiency in System Verilog, UVM, and verification methodologies.
Deep understanding of PCIe Gen3 to Gen6, CXL 1.1 to 3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
Experience using Synopsys/Mentor VIPs, assertion-based verification, coverage-driven testing, and scripting in Perl/Python/Tcl for automation.
Experienced ASIC/Subsystem/SoC verification engineer with 8–12+ years focused on high-speed interconnect protocols and subsystem architectures.
Operates effectively in complex, cross-functional hardware design environments, working closely with design, architecture, and validation teams.
Experienced in verification closure through coverage convergence, assertion-based verification, and mentoring junior engineers in verification methodologies.