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Strong Tier-1 brand, Bengaluru metro, and mid-level (5yr) DV role increase competition despite niche UVM skills.
Specialized DDR DV, UVM/SystemVerilog, and memory-protocol expertise greatly limit cross-industry transferability.
Mandatory 5+ years and specific UVM/SystemVerilog and protocol expertise enforce strict shortlisting.
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Own verification of DDR Subsystem within Infra IP team, including creation of DV infrastructure and integration of VIPs.
Develop and execute detailed test plans, debug verification failures, write assertions, and achieve closure on code and functional coverage.
Collaborate with stakeholders to ensure high quality verification outcomes and overall program success.
Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field is mandatory.
5+ years of Hardware Engineering or related work experience required.
Strong skills in UVM, System Verilog, debugging, and verification methodologies, including testbench development and coverage analysis.
Experience and understanding of LPDDR4/LPDDR5 protocols and bus protocols like AHB/AXI/ACE/ACE-Lite are required.
Experienced in building and navigating complex test benches and verification infrastructures with a methodological approach to bug detection and resolution.
Demonstrated capability to interpret specifications and standards to develop verification test plans effectively.
Skilled in using verification tools and writing scripts to enhance debugging and coverage closure in digital design verification.