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Tier-1 brand and Bangalore location increase competition, but niche EDA+LLM specialization limits applicant pool.
High - specialized semiconductor RTL/EDA domain knowledge required, limiting cross-industry transferability.
High - explicit 6+ years requirement, semiconductor domain expertise, and mandatory Python and agentic AI experience.
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Develop AI-based automation tools to optimize RTL front-end design and verification (DV) workflows including automation of analysis, checks, and flow tasks.
Build and maintain agentic AI workflows using modern open-source frameworks such as LangChain or CrewAI, integrating with existing hardware engineering design flows.
Write and maintain Python scripts with best practices to support AI-driven RTL-to-GDS design automation and continuously adopt new AI tools and practices.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field plus 6+ years related hardware engineering experience; OR Master's degree plus 5+ years experience; OR PhD plus 4+ years experience.
Strong hands-on Python scripting and automation experience with ability to write and review code.
Basic understanding of VLSI front-end flows including RTL, design checks, synthesis, static timing analysis (STA), CDC, formal verification, and design verification (DV).
Practical familiarity with agentic AI frameworks and tooling such as LangChain, CrewAI, LangGraph or similar open-source AI workflow stacks.
Experienced in hardware engineering or RTL front-end design with solid knowledge of VLSI design flows and automation.
Comfortable working independently in a fast-evolving AI tooling ecosystem, iterating quickly on AI-driven automation for hardware design processes.
Skilled in integrating AI-based multi-agent systems and LLM-driven techniques in production-quality RTL/SystemVerilog environments, with scripting automation tightly coupled to engineering workflows.