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Specialized SV/UVM ASIC verification skills lower applicant pool but Tier-1 brand increases interest.
ASIC/SoC verification skills are highly domain-specific and not easily transferable across industries.
Explicit 7+ years requirement plus mandatory SV/UVM, MBIST, ATE and scripting skills increases filter strictness.
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Create and execute SoC verification plans using SystemVerilog/UVM for SoC, Test controller, MBIST, and functional vectors.
Develop verification environments, including SV/UVM monitors, and automate verification flow development.
Collaborate with Architecture, Design, and Tester teams to support vector bring-up and functional characterization on ATE/Tester platforms.
Bachelor's or Master's degree in Engineering.
At least 7 years of SoC/IP verification experience with SystemVerilog/UVM.
Proficient with scripting languages such as Python, Perl, TCL.
Experience in ASIC test vector development, functional characterization on silicon/wafer, and knowledge of Test controller/MBIST/DFT architectures.
Experienced in developing constrained random testing and debugging verification environments in complex SoC architectures.
Familiar with industry-standard interfaces like PCIE, LPDDR, ONFI/NAND to support verification needs.
Demonstrates ability to drive automation and collaborate cross-functionally with Architecture, Design, and Testing teams.