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Tier-1 employer and Bangalore location increase competition, but niche verification skills and seniority reduce applicant density.
Highly specialized SoC and verification methodology skills limit transferability across industries.
Explicit 8+ years requirement plus mandatory SystemVerilog/UVM/UPF and SoC verification experience enforces strict filtering.
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Lead pre-silicon design verification for complex SoC or subsystem designs from strategy to closure.
Define and implement verification methodologies including UVM-based testbenches, functional and code coverage closure, formal verification, and power-aware verification.
Work cross-functionally with emulation, FPGA, firmware teams and influence verification practices within business units and across the company.
B.Tech or M.Tech degree.
8+ years of experience in digital pre-silicon verification.
Proficiency in Verilog/SystemVerilog, UVM, and verification methodologies including functional and code coverage.
Experience with NoC/interconnect verification, power-aware verification (UPF), formal verification, gate-level simulations, and scripting (Python/TCL/Shell).
Experienced in leading complex SoC or subsystem verification projects with a track record of driving verification closure.
Strong expertise in verification architecture and methodology development, capable of influencing cross-business unit practices.
Familiarity with processor-based systems (ARM, RISC-V), AI/ML architectures, and cross-functional collaboration in global engineering teams.