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Tier-1 semiconductor brand and metro location raise applicant density despite niche mixed-signal verification skill.
Highly specialized mixed-signal verification skills limit cross-industry transferability.
Multiple mandatory technical skills and 7+ years experience create strict shortlisting filters.
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Lead design verification strategy for complex analog and mixed-signal digital designs, focusing on verification environment architecture and comprehensive test coverage.
Mentor and provide technical leadership to junior engineers; drive verification methodology adoption and cross-functional collaboration to meet verification requirements and sign-off criteria.
Lead complex debugging efforts at RTL and gate-level, manage functional and code coverage closure, and support post-silicon validation and customer technical interactions.
7-10+ years of relevant digital design verification experience with emphasis on mixed-signal verification.
Expert-level proficiency in SystemVerilog and UVM, with advanced debugging skills and extensive experience with EDA tools (Cadence/Synopsys).
Advanced scripting skills in Python, Perl, TCL, or Shell for verification automation.
MS/PhD in Electrical Engineering, Computer Engineering, or related field.
Experienced technical leader capable of architecting sophisticated UVM-based verification environments for complex mixed-signal systems.
Strong cross-functional collaborator able to coordinate verification strategies across teams and guide junior engineers through mentorship.
Proven ability to drive verification methodology adoption, manage high-impact debugging tasks, and engage effectively with customers and industry partners.