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Medium due to Tier-1 brand and metro location, but niche verification skillset limits applicant pool.
High because SoC verification and post-silicon debug are highly specialized and industry-specific.
High because JD mandates 4 years plus specific SoC verification, Palladium, PCIe/NVMe and C-based skills.
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Lead SoC level verification and IP integration verification including testbench architecture and test development.
Contribute to post silicon validation support including pattern generation, debugging failures, and root cause analysis.
Collaborate closely with validation, firmware teams, and cross-organizational teams to track and close bugs and support SOC bring-up and Pre/Post Silicon validation.
Bachelor's degree in Engineering (B.E/B.Tech).
Minimum 4 years of experience in SoC verification and post silicon debug.
Experience in C based SoC verification methodologies and PCIe transport and link layers and/or NVME architecture.
Work Experience Required: 4 years in SoC verification/post silicon debug.
Experienced in complex SoC verification and post silicon validation in fast-paced environments.
Demonstrated ability to manage verification methodologies and optimize verification flow and turnaround time.
Ability to collaborate effectively with cross-functional teams and troubleshoot complex technical problems.