Back
Strong Tier-1 employer and Bangalore metro location increase competition among qualified candidates.
Specialized RTL and formal methods expertise makes the role highly domain-specific and less transferable.
Explicit 8+ years, 5+ years formal experience, and mandatory tool/RTL expertise make filters strict.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own and maintain the end-to-end formal verification flow integrated within the broader verification process.
Develop formal verification plans, assertions, assumptions, and cover properties to prove key design behaviors and catch bugs missed by simulation.
Mentor and train team members in formal methods, debug failures, and collaborate closely with design teams to improve RTL quality early.
8+ years industry experience in digital design or verification, with at least 5 years focused on formal verification techniques.
Hands-on experience with Verilog or SystemVerilog and complex RTL debugging.
Solid understanding of temporal logic, assertion-based verification (SVA or PSL), and experience with formal tools like Jasper or VC-Formal.
Bachelor's or master's degree in computer science or electrical engineering.
Experienced in tracing formal proof failures to root causes in RTL or verification environment and pushing back on incomplete verification assumptions.
Able to clearly communicate formal verification concepts to non-formal users and work collaboratively with geographically distributed teams.
Organized in managing multiple formal verification tasks and effective in mentoring junior engineers on strategic formal methods thinking.