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Strong employer brand and metro location create moderate applicant density.
Specialized semiconductor verification skills (SystemVerilog/UVM, IP verification) are not easily transferable across industries.
Role mandates senior experience and specific SystemVerilog/UVM and protocol expertise, so filtering is strict.
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Lead and execute unit and IP level design verification using coverage driven constraint random verification methodologies.
Develop and maintain testbenches including stimulus, agents, monitors, and checkers using SystemVerilog and UVM.
Work with C-based reference models inside testbenches and utilize scripting languages like Perl and Python for automation and testing support.
9+ years of experience in unit and IP level hardware design verification.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years experience, or Master's with 3+ years, or PhD with 2+ years of related hardware engineering work.
Strong knowledge of SystemVerilog, UVM, and test planning.
Familiarity with standard protocols such as PCIe, CXL, USB, and Ethernet; experience with coverage driven constraint random verification and C-based reference model integration in testbenches.
Experienced at comprehensive verification of hardware IP blocks in complex SoC designs with proven ability to lead verification efforts.
Skilled in developing robust testbenches and automated test frameworks leveraging SystemVerilog, UVM, and scripting for efficient coverage closure.
Strong understanding and practical exposure to multiple standard protocols (PCIe, CXL, USB, Ethernet), indicating ability to handle protocol compliance verification.