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Tier-1 brand but niche senior ASIC DFT role reduces applicant density.
Highly specialized ASIC DFT/DV skills limit cross-industry transferability.
Requires 10+ years and mandatory ASIC DFT, SystemVerilog/UVM, and scripting skills.
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Drive high-quality DFT verification by collaborating with front-end RTL and backend physical design teams to understand chip architecture.
Develop thorough test plans and test benches to verify comprehensive DFT architecture supporting ATE screening, in-system test, debug, and diagnostics.
Mentor and provide technical leadership to DFT DV engineers; innovate hardware DFT and test strategies for new silicon device models, including bare die and stacked die.
Bachelor’s or Master’s degree in Electrical or Computer Engineering.
Minimum 10+ years of relevant work experience.
Experience with test plan development and test bench creation for DFT verification using System Verilog.
Proficiency in debugging tools (DVE/Verdi) and scripting languages (Tcl, Python/Perl).
Experienced in complex test planning and verification based on detailed design specifications within silicon chip environments.
Skilled in both design and verification collaboration, from pre-silicon through post-silicon validation.
Familiar with advanced DFT methodologies including JTAG, scan architecture, MBIST, boundary scan, and UVM preferred.