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Strong employer brand and metro location but niche hardware verification skills moderate competition.
Requires specialized semiconductor verification skills, limiting transferability across industries.
Explicit mandatory UVM/SystemVerilog and hardware verification lifecycle requirements increase shortlisting strictness.
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Own the full verification life-cycle for AI/ML TPU digital design blocks including verification planning, test execution, and coverage closure.
Develop constrained-random verification environments using SystemVerilog and UVM to detect corner-case bugs ensuring TPU reliability for AI/ML workloads.
Collaborate with design and verification engineers to plan verification scenarios, debug tests, and measure progress towards tape-out.
Bachelor's degree in Electrical Engineering or equivalent practical experience.
At least 1 year of experience with verification methodologies such as UVM, and verification of IP designs like SoC, vector CPUs, or similar.
Proficiency in SystemVerilog, SVA, and functional coverage.
Work Experience Required: Minimum 1 year in related design verification roles.
Experienced in verification of AI/ML accelerator hardware, preferably TPU or vector processing units, with exposure to full verification life-cycle.
Comfortable working in collaboration with cross-functional engineering teams on complex digital hardware validation.
Capable of building and using constrained-random verification environments to achieve high coverage and reliability standards in AI/ML silicon design.