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Niche ASIC verification skills but Pune metro and mid-level seniority increase applicant density.
Highly specialized ASIC verification and semiconductor domain skills limit cross-industry transferability.
Explicit 5+ years plus mandatory SystemVerilog/UVM, EDA tools and scripting imply strict candidate filters.
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Develop and maintain SystemVerilog/UVM based test benches for digital IP blocks including circuit calibration, DSP, and CPU subsystems.
Create and manage constrained random stimulus, assertions, and checkers; analyze simulation data to debug and root cause issues.
Collaborate with digital IP design teams to validate use cases and implement power intent verification using methodologies like UPF; use scripting and agentic AI tools to improve efficiency and automation across silicon development lifecycle.
Bachelor's degree in Electrical Engineering or equivalent; Master's degree is a plus.
5+ years of hardware engineering experience focusing on SystemVerilog test bench development and UVM methodology.
Proficiency in scripting languages such as Python, Perl, or Tcl; experience with EDA tools including digital simulators, waveform viewers, and automation tools.
Knowledge of digital logic design, CPU architectures and microarchitectures; communication skills required.
Experienced in developing scalable and portable test benches using UVM and SystemVerilog in wireless communication ASIC context.
Able to work independently on problem-solving and collaborate effectively with cross-functional design teams.
Familiar with verification methodologies including power intent verification (UPF), advanced techniques like formal verification and assertions, and skilled in scripting to automate silicon development tasks.