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Mid-level, metro, and generalist title but niche EDA skills reduce applicant density.
Highly specialized ASIC/EDA skills limit cross-industry transferability.
Mandatory EDA tool expertise and explicit 2+ years plus domain-specific PPA requirements increase screening strictness.
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Develop, automate, and maintain EDA flows and scripts for physical implementation in advanced process nodes.
Optimize power, performance, and area (PPA) for IPs and soft controllers across multiple foundries including TSMC, Intel, Samsung, and Rapidus.
Manage regression infrastructure monitoring RTL/flow quality and key design PPA; perform digital design implementation using Cadence EDA tools and develop AI-based automation scripts to reduce design turnaround time.
MS/MTech/BE/BTech in Electronics from reputed institutes.
2+ years of experience in ASIC physical design environment.
Strong knowledge of complete ASIC design flow: synthesis, physical design, timing analysis, power analysis, and formal verification.
Proficiency in EDA tools like Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus; solid scripting skills in Python and Tcl.
Experienced in logic synthesis, PPA optimization, and logic equivalence check debugging for production designs.
Demonstrated hands-on skills developing and debugging synthesis flows with tools such as Genus and Fusion Compiler.
Capable of leading tasks with strong communication, analytical, and problem-solving skills, comfortable working in team environments.