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Niche senior VLSI verification role with specialized SystemC/SystemVerilog skills reduces applicant density.
Highly domain-specific VLSI verification skills make cross-industry transfers difficult.
Explicit 13+ years requirement with mandatory SystemC/C++ verification skills enforces strict shortlisting.
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Develop and code C++ and SystemC models along with test creation for functional modeling and verification.
Validate and debug models using SystemC, SystemVerilog, and UVM testbenches, collaborating with cross-functional teams for root cause analysis.
Mentor and lead junior engineers within the team.
13+ years of relevant experience in functional modeling and verification.
Proficiency in C++, SystemC, C-based test/testbench development; Python coding is a plus.
Bachelor's or Master's degree in Electronics and Communication or Embedded Systems from a reputed institute.
Experience with VisualStudio, Git, Bitbucket; knowledge of Verilog/SystemVerilog/UVM is a plus.
Experienced in system-level functional modeling with strong coding skills in C++ and SystemC.
Comfortable leading technical debugging and mentoring junior engineers in a complex VLSI verification environment.
Familiarity with NAND concepts, memory systems (SRAM/DRAM/ROM/Flash), and digital design concepts preferred.