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Tier-1 brand, metro location, and mid-level years increase competition, but niche RTL/EDA skillset moderates it.
Role requires semiconductor verification and RTL/EDA expertise, making backgrounds less transferable across industries.
Explicit years and mandatory CI/CD, EDA, and scheduling tooling indicate strict technical filters.
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Maintain and enhance CI/CD infrastructure for CPU design and verification workflows within the Qualcomm Oryon CPU team.
Collaborate with RTL, DV, and DFT teams and global stakeholders to optimize verification flows and scale infrastructure.
Drive automation, continuous improvement initiatives, and coordinate with EDA vendors for tool-related issue resolution.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years hardware engineering or related experience, OR Master's degree with 3+ years, OR PhD with 2+ years.
Strong experience with Git, GitHub, Python, Shell scripting, and LSF for job scheduling.
Familiarity with CI/CD tools like Jenkins and workflow orchestration tools such as Airflow.
Work Experience Required: Minimum 2 to 4 years hardware engineering or related work experience depending on degree.
Proven ability to manage and optimize verification infrastructure and workflows in CPU design domain.
Experience collaborating cross-functionally with RTL, DV, DFT teams and global stakeholders in a complex engineering environment.
Strong technical expertise in CI/CD infrastructure management and scripting with a background in hardware engineering or CPU microarchitecture.