Back
Niche EDA specialization reduces applicants, but metro location and mid-level seniority increase competition.
Highly domain-specific semiconductor EDA skills limit transferability across industries.
Requires 6+ years, Cadence Voltus expertise, IR/EM signoff experience and export-eligibility checks.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own block-level and full-chip static and dynamic IR/EM analysis flow and methodology including Out-of-Context and In-Context block-level IR signoff.
Develop and automate PSI signoff flows (using Tcl, Python) supporting tapeout activities and ensuring IR/EM signoff closure.
Collaborate with EDA vendors to evaluate and improve tool capabilities and lead knowledge sharing and training on IR/EM CAD flows globally.
B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or related field.
6+ years of hands-on experience with Cadence Voltus for IR drop and EM analysis in production ASIC/SoC flows.
Proven experience running block-level and full-chip PSI signoff on advanced nodes (7nm, 5nm, or 3nm).
Must be eligible to access export-controlled technology/software per U.S. export laws (e.g., EAR).
Strong expertise in static and dynamic power and IR analysis methodology including hierarchical and package-aware IR simulation.
Experienced in interfacing with EDA vendors and driving tool and methodology improvements.
Proficient in automation scripting to streamline complex IR/EM flows and support cross-functional tapeout collaboration within global teams.