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Tier‑1 semiconductor brand and Bangalore location increase candidate density despite niche DFT specialization.
Highly specialized semiconductor DFT methodology and EDA tool expertise limits cross-industry transferability.
Specific 8–12 years requirement, mandatory DFT/EDA tools, scripting skills, and export-control eligibility increase filter strictness.
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Lead and manage the DFT methodology team responsible for flows and DFT/DFX solutions on complex IP and SoC designs for Custom and Compute ASICs/SoCs.
Drive development and support of DFT methodologies including SCAN-Insertion, MBIST, ATPG, Validation, STA, IP-DFT, pattern generation, post-silicon bring-up, and debug.
Define and enhance DFT methodologies and tools while managing and mentoring a team to scale efforts across multiple designs.
Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related fields.
8 to 12 years of related professional experience.
Working experience with DFT methodology development and familiarity with tools such as Siemens Tessent, Spyglass, Tmax, DC, Genus, or Modus.
Scripting skills in PERL, Tcl-tck, or C-Shell required.
Strong expertise in digital circuit design and logic design with prior ASIC design experience preferred.
Experienced in managing and mentoring engineering teams within DFT or semiconductor design environments.
Proven ability to drive technical methodology development and implement complex DFT/DFX flows in advanced SoC designs.