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Niche hardware verification skills and seniority sharply reduce qualified applicant density despite metro location.
Highly specialized semiconductor verification skills are not easily transferable across industries.
Explicit 15-year minimum and mandatory SystemVerilog/UVM/Formal expertise create strict screening filters.
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Lead IP-level verification for dsPIC products, including architecture, development, and maintenance of UVM and Formal verification environments.
Define and implement verification plans with constrained-random UVM Testbenches and Formal Testbenches, develop assertions and coverage, debug RTL and testbench issues.
Collaborate across global design, architecture, and SoC teams to ensure quality results and timely project delivery; provide technical mentoring and drive methodology improvements including AI/ML automation.
Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering or related field.
Minimum 15 years of experience in functional verification.
Strong expertise in SystemVerilog, assertions, and UVM methodology; experience in building IP-level and SoC-level verification environments using UVM and/or formal verification.
Understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
Experienced technical leader with track record of mentoring and leading verification engineers across global teams.
Capable of driving verification methodology improvements and automation initiatives.
Able to work collaboratively with cross-functional global teams and manage complex verification projects with a focus on quality and timely delivery.