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Senior niche semiconductor role at strong Tier-1 company reduces applicant density to medium.
Highly specialized semiconductor verification skills transfer poorly outside chip design industry.
Mandatory 12+ years, UVM/SystemVerilog expertise and SoC analog knowledge make filters highly strict.
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Own and define verification plans, methodologies, and coverage strategies for complex SoC designs including block-level to full-chip verification.
Architect and implement verification environments from scratch; build and integrate verification components like agents, sequences, drivers, monitors, and scoreboards.
Lead end-to-end verification activities including gate-level simulations, coverage closure, regression, triage failures, and deliver quality sign-off; mentor junior engineers.
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Minimum 12 years of experience with verification methodologies such as UVM and working with industry-standard simulators and regression systems.
Experience in architecting full verification lifecycle for SoC and block designs including testbench development and debugging RTL/Gate simulations.
Working knowledge of scripting languages (Perl, Python) and proficiency in UVM, Verilog, SystemVerilog, C/C++, Shell.
Senior engineer experienced in delivering complex SoC verification solutions in semiconductor embedded systems, especially power management SoCs.
Practitioner with strong expertise in building automated, scalable verification frameworks following UVM and mixed-signal verification experience including analog components (ADC, DAC, PLL).
Technical leader capable of managing verification deliverables, mentoring teams, and collaborating cross-functionally for defect triaging and quality assurance.