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Niche hardware verification skillset and senior requirement reduce applicant density despite recognizable semiconductor employer.
Highly specialized RTL/UVM verification skills limit transferability across industries.
Explicit 15-year requirement and mandatory SystemVerilog/UVM make filters highly restrictive.
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Lead IP-level verification for dsPIC products using formal verification and UVM testbenches.
Architect, develop, and maintain UVM and formal verification environments; define verification plans.
Collaborate globally across design, architecture, and SoC teams to deliver quality verification results on schedule, including mentoring verification engineers and improving methodologies with AI/ML automation.
Bachelor’s or master’s degree in Electrical, Electronics, or Computer Engineering or related field.
Minimum 15 years of experience in functional verification.
Strong expertise with SystemVerilog, assertions, and UVM methodology; proven experience with IP- and SoC-level verification environments.
Understanding of digital design, RTL fundamentals, ARM/RISC SoC architectures.
Experienced leader capable of driving and mentoring verification efforts in a global team and cross-functional environment.
Technical expert in formal and constrained-random UVM verification methodologies with IP and SoC verification focus.
Able to leverage AI/ML for verification automation and cycle time reduction, maintaining high-quality deliverables on schedule.